1. Field of the Invention
The present invention relates to a parallel processing technique to perform high-speed processing with a plurality of processors connected to each other, and more particularly, to a multiprocessor system allowing reduction of power consumption and a control method thereof.
2. Description of the Background Art
In recent years, there has been an increasing demand for improved processor performance in a variety of fields including multimedia processing and high-definition image processing. With the current LSI (large-scale integrated circuit) manufacturing techniques, however, there is a limit for speeding up of devices. Thus, parallel processing has attracted attention, and research and development of multiprocessor systems have vigorously been made.
Generally, when a plurality of processors are used for parallel processing to perform one processing, loads should be distributed to the processors as evenly as possible so as to obtain maximum performance of the entire system. In practical application designing, however, such uniform load distribution cannot necessarily be achieved when considering simplification of development, reduction of system cost and others. Thus, there often occurs a situation where one processor needs to wait for completion of processing of another processor.
There also exists a demand for reduced power consumption of a system for elongation of life of batteries mounted on portable equipment and for consideration for a recently advocated environmental issue. One way to reduce the power consumption of the system is to decrease a clock frequency for a part or a whole of the system according to an operating situation of the system.
FIG. 1 illustrates an example of such reduction of power consumption in a conventional multiprocessor system. This multiprocessor system includes a first processor 101, a second processor 102, a memory 103 storing a first program, a memory 104 storing a second program, and a clock supply control unit 105 controlling supply and stoppage of supply of a clock to first processor 101.
In the case where first processor 101 executes the first program stored in memory 103 and second processor 102 executes the second program stored in memory 104, assume that the processing time of first processor 101 is shorter than the processing time of second processor 102. In this case, these two processors are synchronized by causing first processor 101 to wait for the completion of the processing of second processor 102 at the end of the execution of the first program.
In such a system, if first processor 101 does not need to execute any processing until second processor 102 completes the processing, it would issue a control command to clock supply control unit 105 to force it to stop the clock supply to first processor 101 so as to reduce the power consumption of first processor 101.
In the multiprocessor system as described above, it may be possible to reduce the power consumption during the period from the time when first processor 101 completes its processing to the time when second processor 102 completes its processing, by stopping the clock supply to first processor 101. However, further reduction of power consumption cannot be expected.